Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits PDF Download
Are you looking for read ebook online? Search for your book and save it on your Kindle device, PC, phones or tablets. Download Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits PDF full book. Access full book title Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits by Manoj Sachdev. Download full books in PDF and EPUB format.
Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 0387465472
Category : Technology & Engineering
Languages : en
Pages : 343
Get Book
Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 0387465472
Category : Technology & Engineering
Languages : en
Pages : 343
Get Book
Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Author: Manoj Sachdev
Publisher: Springer
ISBN: 9780387516530
Category : Technology & Engineering
Languages : en
Pages : 328
Get Book
Book Description
The 2nd edition of defect oriented testing has been extensively updated. New chapters on Functional, Parametric Defect Models and Inductive fault Analysis and Yield Engineering have been added to provide a link between defect sources and yield. The chapter on RAM testing has been updated with focus on parametric and SRAM stability testing. Similarly, newer material has been incorporated in digital fault modeling and analog testing chapters. The strength of Defect Oriented Testing for nano-Metric CMOS VLSIs lies in its industrial relevance.
Author: Sachdev
Publisher:
ISBN: 9788184894295
Category :
Languages : en
Pages : 349
Get Book
Book Description
Author: Manoj Sachdev
Publisher: Springer Science & Business Media
ISBN: 1475749260
Category : Technology & Engineering
Languages : en
Pages : 317
Get Book
Book Description
Defect oriented testing is expected to play a significant role in coming generations of technology. Smaller feature sizes and larger die sizes will make ICs more sensitive to defects that can not be modeled by traditional fault modeling approaches. Furthermore, with increased level of integration, an IC may contain diverse building blocks. Such blocks include, digital logic, PLAs, volatile and non-volatile memories, and analog interfaces. For such diverse building blocks, traditional fault modeling and test approaches will become increasingly inadequate. Defect oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits (ICs) have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of highest possible quality. Testing, in general and, defect oriented testing, in particular, help in realizing these objectives. Defect Oriented Testing for CMOS Analog and Digital Circuits is the first book to provide a complete overview of the subject. It is essential reading for all design and test professionals as well as researchers and students working in the field. `A strength of this book is its breadth. Types of designs considered include analog and digital circuits, programmable logic arrays, and memories. Having a fault model does not automatically provide a test. Sometimes, design for testability hardware is necessary. Many design for testability ideas, supported by experimental evidence, are included.' ... from the Foreword by Vishwani D. Agrawal
Author: Andrei Pavlov
Publisher: Springer Science & Business Media
ISBN: 1402083637
Category : Technology & Engineering
Languages : en
Pages : 203
Get Book
Book Description
The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
Author: Haidi Ibrahim
Publisher: Springer
ISBN: 9811017212
Category : Technology & Engineering
Languages : en
Pages : 861
Get Book
Book Description
The proceeding is a collection of research papers presented, at the 9th International Conference on Robotics, Vision, Signal Processing & Power Applications (ROVISP 2016), by researchers, scientists, engineers, academicians as well as industrial professionals from all around the globe to present their research results and development activities for oral or poster presentations. The topics of interest are as follows but are not limited to: • Robotics, Control, Mechatronics and Automation • Vision, Image, and Signal Processing • Artificial Intelligence and Computer Applications • Electronic Design and Applications • Telecommunication Systems and Applications • Power System and Industrial Applications • Engineering Education
Author: George A. Tsihrintzis
Publisher: Springer
ISBN: 3030156281
Category : Technology & Engineering
Languages : en
Pages : 548
Get Book
Book Description
This book is the inaugural volume in the new Springer series on Learning and Analytics in Intelligent Systems. The series aims at providing, in hard-copy and soft-copy form, books on all aspects of learning, analytics, advanced intelligent systems and related technologies. These disciplines are strongly related and mutually complementary; accordingly, the new series encourages an integrated approach to themes and topics in these disciplines, which will result in significant cross-fertilization, research advances and new knowledge creation. To maximize the dissemination of research findings, the series will publish edited books, monographs, handbooks, textbooks and conference proceedings. This book is intended for professors, researchers, scientists, engineers and students. An extensive list of references at the end of each chapter allows readers to probe further into those application areas that interest them most.
Author: Ravi K. Gulati
Publisher: Springer Science & Business Media
ISBN: 1461531462
Category : Computers
Languages : en
Pages : 121
Get Book
Book Description
Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Author: Sandeep K. Goel
Publisher: CRC Press
ISBN: 143982942X
Category : Technology & Engineering
Languages : en
Pages : 259
Get Book
Book Description
Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
Author: Manoj Sachdev
Publisher:
ISBN: 9789074445276
Category : Electric circuits
Languages : en
Pages : 173
Get Book
Book Description
